1. Field of the Invention
The present invention relates to an imaging device and an endoscopic device using the same.
This application claims the benefits of Japanese Patent Application No. 2011-226757, filed Oct. 14, 2011, the disclosure of which is hereby incorporated herein by references in its entirety.
2. Description of Related Art
For imaging devices, various types of imaging devices, such as a MOS (Metal Oxide Semiconductor) type and a CCD (Charge Coupled Device) type, have been proposed and have led to practical use. Further, among the MOS types, there is a (C)MOS-type imaging device including pixels having an amplification type solid-state imaging element (APS: Active Pixel Sensor) configuration that amplifies and outputs a pixel signal corresponding to signal charges generated by a charge generation unit.
First, a configuration of a (C)MOS-type imaging device according to a first conventional example (e.g., see Japanese Patent Unexamined Application, First Publication No. 2000-4399) will be described. FIG. 15 shows a schematic configuration of the (C)MOS-type imaging device according to the first conventional example. An imaging device 1001a shown in FIG. 15 includes an imaging unit 1002, a vertical selection unit 1004, a column circuit unit 1005, a horizontal selection unit 1006, and an output unit 1007.
In the imaging unit 1002, a plurality of pixels 1003 including a charge generation unit PD (e.g., a photodiode), a transfer transistor Tx, a charge accumulation unit FD (e.g., floating diffusion), a reset transistor Rst, an amplification transistor Dry, and a selection transistor Sel are arranged in a matrix shape. In the example of FIG. 15, the imaging unit 1002 includes pixels 1003 (M11, M12, M21 and M22) arranged in two rows and two columns.
The charge generation unit PD generates signal charges corresponding to an amount of an incident electromagnetic wave. The transfer transistor Tx transfers the signal charges generated by the charge generation unit PD to a charge accumulation unit FD. The charge accumulation unit FD accumulates the transferred signal charges. The reset transistor Rst resets the charge accumulation unit FD to a predetermined voltage. The amplification transistor Dry amplifies a signal corresponding to a voltage of the charge accumulation unit FD and generates a pixel signal. The selection transistor Sel outputs the pixel signal to a vertical signal line 1030 arranged in each column of the imaging unit 1002. As is well known, a reset level and a signal level are output as the pixel signal from the pixel 1003.
The transfer transistor Tx is controlled by a transfer pulse output from the vertical selection unit 1004.
In FIG. 15, it is assumed that a transfer pulse output to the pixels 1003 (M11 and M12) of a first row is φTx_1 and a transfer pulse output to the pixels 1003 (M21 and M22) of the second row is φTx_2. The reset transistor Rst is controlled by a reset pulse output from the vertical selection unit 1004. In FIG. 15, it is assumed that a reset pulse output to the pixels 1003 (M11 and M12) of the first row is φRst_1, and a reset pulse output to the pixels 1003 (M21 and M22) of the second row is φRst_2. The selection transistor Sel is controlled by a selection pulse output from the vertical selection unit 1004. In FIG. 15, it is assumed that the selection pulse output to the pixels 1003 (M11 and M12) of the first row is φSel_1, and the selection pulse output to the pixels 1003 (M21 and M22) of the second row is φSel_2.
The vertical selection unit 1004 selects the plurality of pixels 1003 arranged in a row direction of the imaging unit 1002, and controls an operation of the selected pixels 1003. The column circuit unit 1005 is arranged in each column and connected to the vertical signal line 1030. The column circuit unit 1005 includes a load transistor SW1, switch transistors SW2, SW3, SW4, and SW5, and capacitive elements CR and CS. The pixel signals at the reset level and the signal level are held in the capacitive elements CR and CS, respectively.
The load transistor SW1 is biased by a bias voltage LMB. The switch transistors SW2 and SW3 are controlled by control pulses φSHR and φSHS, respectively, and turned on when the pixel signals at the reset level and the pixel signal at the signal level are transferred. The switch transistors SW4 and SW5 are controlled for each column. The switch transistor SW4 is connected to a horizontal signal line 1031 connected to the output unit 1007, and the switch transistor SW5 is connected to a horizontal signal line 1032 connected to the output unit 1007.
The switch transistors SW4 and SW5 of the first column are controlled by a selection pulse HSR[0] output from the horizontal selection unit 1006, and turned on when the pixel signal at the reset level and the pixel signal at the signal level held in the capacitive elements CR and CS of the first column are transferred. The switch transistors SW4 and SW5 of the second column are controlled by a selection pulse HSR[1] output from the horizontal selection unit 1006, and turned on when the pixel signal at the reset level and the pixel signal at the signal level held in the capacitive elements CR and CS of the second column are transferred. The horizontal selection unit 1006 sequentially selects the switch transistors SW4 and SW5 using the selection pulses HSR[0] and HSR[1] and transfers the pixel signals held in the capacitive elements CR and CS to the output unit 1007. The output unit 1007 outputs the transferred pixel signal to a circuit of a subsequent stage.
Next, an operation of the (C)MOS-type imaging device according to the first conventional example will be described. FIG. 16 shows an operation of the (C)MOS-type imaging device according to the first conventional example. First, as the selection pulse φSel_1 output to the pixel 1003 of the first row is changed from being in an L (Low) state to being in an H (High) state, the selection transistor Sel is turned ON (a conduction state) and the pixel 1003 of the first row is selected. At substantially the same time, as the reset pulse φRst_1 output to the pixel 1003 of the first row is changed from the L state to the H state, the reset transistor Rst is turned ON, the charge accumulation unit FD is reset, and the pixel signal at the reset level is output to the vertical signal line 1030.
Then, as the reset pulse φRst_1 is changed from being in the H state to being in the L state, the reset transistor Rst is turned OFF (a non-conduction state). At substantially the same time, the control pulse φSHR output to the switch transistor SW2 is changed from being in the L state to being in the H state, the switch transistor SW2 is turned ON, and the pixel signal at the reset level of the pixels 1003 (M11 and M12) of the first row is held in the capacitive element CR.
Then, as the control pulse φSHR is changed from being in the H state to being in the L state, the switch transistor SW2 is turned OFF. At substantially the same time, as the transfer pulse φTx_1 output to the pixel 1003 of the first row is changed from being in the L state to being in the H state, the transfer transistor Tx is turned ON, the signal charges of the charge generation unit PD are transferred to the charge accumulation unit FD, and the pixel signal at the signal level is output to the vertical signal line 1030.
Then, as the transfer pulse φTX_1 is changed from being in the H state to being in the L state, the transfer transistor Tx is turned OFF. At substantially the same time, as the control pulse φSHS output to the switch transistor SW3 is changed from being in the L state to being in the H state, the switch transistor SW3 is turned ON, and the pixel signal at the signal level output from the pixels 1003 (M11 and M12) of the first row is held in the capacitive element CS.
Then, as the control pulse φSHS is changed from being in the H state to being in the L state, the switch transistor SW3 is turned OFF, and as the selection pulse φSel_1 output to the pixel 1003 of the first row is changed from being in the H state to being in the L state, the selection transistor Sel is turned OFF. At substantially the same time, as the selection pulse HSR[0] output to the switch transistors SW4 and SW5 of the first column is changed from being in the L state to being in the H state, the switch transistors SW4 and SW5 are turned ON, the pixel signal at the reset level held in the capacitive element CR of the pixel 1003 (M11) of the first row and the first column is output to the horizontal signal line 1031, and the pixel signal at the signal level held in the capacitive element CS of the pixel 1003 (M11) of the first row and the first column is output to the horizontal signal line 1032. The pixel signals at the reset level and the signal level are input to the output unit 1007, and, for example, a signal corresponding to a difference between the reset level and the signal level is output from the output unit 1007.
Then, as the selection pulse HSR[0] is changed from being in the H state to being in the L state, the switch transistors SW4 and SW5 are turned OFF. At substantially the same time, as the selection pulse HSR[1] output to the switch transistors SW4 and SW5 of the second column is changed from being in the L state to being in the H state, the switch transistors SW4 and SW5 are turned ON. The pixel signal at the reset level of the pixel 1003 (M12) of the first row and the second column held in the capacitive element CR is output to the horizontal signal line 1031, and the pixel signal at the signal level of the pixel 1003 (M12) of the first row and the second column held in the capacitive element CS is output to the horizontal signal line 1032. The pixel signals at the reset level and the signal level are input to the output unit 1007, and, for example, a signal corresponding to a difference between the reset level and the signal level is output from the output unit 1007.
Then, as the selection pulse HSR[1] is changed from being in the H state to being in the L state, the switch transistors SW4 and SW5 are turned OFF and an operation of reading the pixel signal from the pixel 1003 of the first row ends. An operation of reading a pixel signal from the pixel 1003 of the second row is then performed, similar to the operation of reading the pixel signal from the pixels 1003 of the first row.
Next, a configuration of a (C)MOS-type imaging device according to a second conventional example (e.g., see Japanese Unexamined Patent Application, First Publication No. 2001-8109) will be described. FIG. 17 shows a schematic configuration of the (C)MOS-type imaging device according to the second conventional example.
An imaging device 1001b shown in FIG. 17 includes an imaging unit 1002, a vertical selection unit 1004, a switch unit 1008, a horizontal selection unit 1006, and an output unit 1009.
Configurations of the imaging unit 1002, the vertical selection unit 1004, and the horizontal selection unit 1006 are substantially similar to those in FIG. 15. However, in a pixel 1003, a control transistor Cnt_for controlling a transfer transistor Tx is added. The control transistor Cnt is controlled by a selection pulse output from the vertical selection unit 1004. Further, the transfer transistor Tx is controlled by a transfer pulse output from the horizontal selection unit 1006. A transfer pulse φCnt_1 is output from the horizontal selection unit 1006 to the transfer transistor Tx in the pixel 1003 of a first column, and a transfer pulse φCnt_2 is output from the horizontal selection unit 1006 to the transfer transistor Tx in the pixel 1003 of a second column.
The switch unit 1008 includes a switch transistor SW arranged in each column. The switch transistor SW is connected to a vertical signal line 1030 and a horizontal signal line 1031, and outputs a pixel signal output to the vertical signal line 1030, to the horizontal signal line 1031. The switch transistor SW of the first column is controlled by a selection pulse HSR[0] output from the horizontal selection unit 1006, and the switch transistor SW of the second column is controlled by a selection pulse HSR[1] output from the horizontal selection unit 1006. The horizontal signal line 1031 is connected to the output unit 1009. The horizontal selection unit 1006 sequentially selects the switch transistors SW using the selection pulses HSR[0] and HSR[1] to transfer the pixel signal to the output unit 1009. This pixel signal is input to the output unit 1009 as a current signal. The output unit 1009 converts the pixel signal to a voltage signal, and outputs the voltage signal to the circuit of the subsequent stage.
Next, an operation of the (C)MOS-type imaging device according to the second conventional example will be described. FIG. 18 shows an operation of the (C)MOS-type imaging device according to the second conventional example. First, as a selection pulse φSel_1 output to the pixel 1003 of the first row is changed from being in the L state to being in the H state, a selection transistor Sel and the control transistor Cnt are turned ON and the pixel 1003 of the first row is selected. At substantially the same time, as a reset pulse φRst_1 output to the pixel 1003 of the first row is changed from being in the L state to being in the H state, the reset transistor Rst is turned ON, a charge accumulation unit FD is reset, and the pixel signal at the reset level is output to the vertical signal line 1030. At substantially the same time, as the selection pulse HSR[0] output to the switch transistor SW of the first column is changed from being in the L state to being in the H state, the switch transistor SW is turned ON, the pixel signal at the reset level of the pixel 1003 (M11) of the first row and the first column output to the vertical signal line 1030 is output to the horizontal signal line 1031 and input to the output unit 1009. The output unit 1009 converts the pixel signal at the reset level input as a current signal into a voltage signal, and outputs the voltage signal to the circuit of the subsequent stage.
Then, as the reset pulse φRst_1 is changed from being in the H state to being in the L state, the reset transistor Rst is turned OFF. Then, as the control pulse φCnt_1 output to the transfer transistor Tx of the first column is changed from being in the L state to being in the H state, the transfer transistor Tx is turned ON, signal charges of the charge generation unit PD are transferred to the charge accumulation unit FD, and the pixel signal at the signal level is output to the vertical signal line 1030. Since the selection pulse HSR[0] output to the switch transistor SW of the first column is in an H state and the switch transistor SW is turned ON, the pixel signal at the signal level of the pixel 1003 (M11) of the first row and the first column output to the vertical signal line 1030 is output to the horizontal signal line 1031 and input to the output unit 1009. The output unit 1009 converts the pixel signal at the signal level input as a current signal into a voltage signal, and outputs the voltage signal to the circuit of the subsequent stage.
Then, as the transfer pulse φCnt_1 is changed from being in the H state to being in the L state, the transfer transistor Cnt is turned OFF. Then, as the selection pulse HSR[0] is changed from being in the H state to being in the L state, the switch transistor SW is turned OFF and the operation of reading the pixel signal from the pixel 1003 of the first row and the first column ends.
The operation of reading the pixel signal from the pixel 1003 (M12) of the first row and the second column is then performed. Since the operation of reading the pixel signal from the pixel 1003 of the first row and the second column is similar to the operation of reading the pixel signal from the pixel 1003 of the first row and the first column except that the switch transistor SW of the second column is selected by the transfer pulse HSR[1] instead of the transfer pulse HSR[0], a description thereof will be omitted. As the selection pulse φSel_1 is changed from being in the H state to being in the L state, the selection transistor Sel and the control transistor Cnt_are turned OFF and the operation of reading a pixel signal from the pixel 1003 of the first row ends. An operation of reading a pixel signal from the pixel 1003 of the second row is then performed. Since an operation of reading a pixel signal from the pixel 1003 of the second row is similar to the operation of reading a pixel signal from the pixel 1003 of the first row except that the pixel 1003 of the second row is selected by the selection pulse φSel_2 instead of the selection pulse φSel_1, a description thereof will be omitted. Lastly, the circuit of the subsequent stage acquires a signal component (a signal corresponding to a difference between the reset level and the signal level) by performing subtraction (a CDS process).